1. Field of the Invention
This invention relates to the field of recovering clock and data information from serial data that has been phase-encoded for subsequent digital processing in an integrated circuit, and, in particular, for metal oxide semiconductor (MOS) circuits.
2. Art Background
It is quite common for data communication equipment to transmit and receive serial data that has been phase-encoded. Phase-encoded data is data that has the synchronization information (i.e., clock) encoded together with the data in a single stream of pulses or frames. Because the clock and data information is combined, only a single transmission medium, for example, co-axial cable, twisted pair, or optic fiber, is required to transmit the data from point to point. Circuits that recover clock and data information from a phase-encoded serial data are most useful where the clock frequencies of the transmitting equipment and that of the receiving equipment are matched to a small tolerance. This stringent requirement is incorporated in Local Area Network (LAN) data communication standards such as Carrier-Sense-Multiple Access with Collision Detection (CSMA/CD) and Fiber Distributed Data Interface (FDDI). Phase-encoded serial data is also used in data transfer between disk memories and host computers.
Two common methods are used to recover data and clock information from phase-encoded serial data: the one-shot method and the phase-locked loop (PLL) method. The one-shot method is simple to implement but has poor tolerance to phase jitter. The phase-locked loop method has good tolerance to phase jitter but is difficult to implement. Phase jitter is the variation in the location of transitions of a stream of pulses or frames from bit to bit. The tolerance to phase jitter is defined as the permitted range of time over which a transition can still be received correctly, divided by the data bit-cell period. Hence, the phase-jitter tolerance is measured as a fraction of a bit time. In the case of the one-shot method, the theoretical upper bound in phase jitter tolerance is .+-.1/8 bit time, although practical implementation limitations reduce this tolerance even further. In contrast, the upper bound in phase-jitter tolerance of the PLL method is .+-.1/4 bit time. The greatest disadvantage of the PLL method, however, is its sensitivity to parameter variations, and, as such, it is difficult to manufacture in MOS on account of the large variability of the MOS technology. Thus, implementing the PLL method in MOS requires the delicate trade-off between maintaining the stability of the PLL and achieving maximum phase jitter tolerance. Finally, the PLL method requires additional circuitry to ensure the correct masking operation is performed in recovering the clock information from the phase-encoded data. In a masking operation, a mask bit is combined with the phase-encoded data to extract the locations of the transition of the phase-encoded data. Under the PLL method, a special lockon enabling signal is required. In contrast, the one-shot method achieves lockon automatically.
It is an object of the present invention to recover digital clock and data information from phase-encoded serial data with the maximum phase-jitter tolerance but without the sensitivity to variation in processing, temperature and supply.
It is another object of the present invention to implement the recovery of clock and data information from a phase-encoded serial data in a MOS circuit.
It is yet another object of the present invention to achieve lockon rapidly while immunizing the invention from variations in processing temperature or voltage supply.